Begining in 1998, workshops dedicated to a special field were incorporated to the programme of the MIDEM Conferences. During the workshop, five to seven invited speakers present papers on the chosen topics from different aspects within their special field, thus offering the audience valuable information. Time for thorough discussions is provided between invited presentations. Conference attendees are encouraged to present their research results in the Conference session dealing with the dedicated topic. Attendance at the workshop is included in the Conference registration fee.

For the year 2003, we are pleased to announce a

This year, the workshop is focused on the embedded systems which are rapidly becoming one of the driving factors in the electronic industry. The workshop will cover a broad scope of embedded systems, from the embedded systems architecture, systems-on-chip (SoC) embedded systems, embedded systems design cases, to the current trends in embedded systems test and software development cycle.

The workshop is organized by the Electronics Department of the Faculty of Electrical Engineering, University of Ljubljana.

The programme committee is pleased to announce the following invited speakers, who will give their presentations on the following subjects:

Reiner Hartenstein,
Kaiserslautern University of Technology, Kaiserslautern, Germany

Data-Stream-Based Computing: Models and Architectural Resources

Embedded System Design often turns hardware / software co-design into hardware / configware / software co-design. The transition from HDL languages to sources of higher abstraction levels, like System-C and others, encourages to go from complex design flows to compilation techniques which are supported by a simple machine paradigm model. Because the instruction-stream-based von Neumann mind set does not support configware compilation we need a data-stream-based second model, which has been popularized recently by a number of projects in reconfigurable computing, and even for a hardwired solution. The paper introduces this anti machine model and its architectural resources in detail.

Juergen Becker,
Universitaet Karlsruhe (TH), Institut für Technik der Informationsverarbeitung (ITIV), Germany

Configurability for Systems on Silicon: Requirement and Perspective for future VLSI Solutions

Systems-on-Chip (SoC) has become reality now, driven by fast development of CMOS VLSI technologies. Complex system integration onto one single die introduce a set of various challenges and perspectives for industrial and academic institutions. Important issues to be addressed here are cost-effective technologies, efficient and application-tailored hardware/software architectures, as well as corresponding IP-based EDA methods. This talk will first provide an overview on recent academic and commercial developments in Configurable Systems-on-Chip (CsoC) architectures, technologies and application perspectives in:

Manfred Ley,
Carinthia Tech Institute, University of Applied Science, Villach, Austria

Distributed Embedded Safety Critical Real-Time Systems:
Design and Verification Aspects on the Example of the Time Triggered Architecture

The Time Triggered Architecture (TTA) and its related communication protocol, TTP/C is an emerging communication principle for distributed fault-tolerant real-time systems. Typical applications are safety-critical digital control systems such as drive-by-wire and fly-by-wire. This paper highlights the hardware / software architecture and design of the first industrial single chip communication controller for the Time Triggered Protocol (TTP/C). An application specific RISC core with several specialized peripheral blocks, RAMs, flash memory and analog cells was implemented together with necessary protocol firmware to fulfil both cost and safety requirements. Whereas the controller chip itself can be seen as an embedded system, the composability characteristic of TTA enables a hierarchical system design style with nodes and communication clusters as higher level system components embedded into an application device like a car or airplane. A complete framework for hardware / software co-simulation and verification across all levels of hierarchy was built up to support the design work from chip to system level. Furthermore, system reliability and fault behaviour of a safety critical system has to be shown to safety certification authorities. Extensive fault injection experiments have been performed at simulation level and physical level to prove the concept, fault model and resulting implementation of an embedded TTA control system.

Franc Novak,
Jozef Stefan Institute, Ljubljana, Slovenia

Current Trends in Embedded System Test

Increasing complexity of electronic components and systems makes testing a challenging task. With the introduction of surface mounted devices, traditional in-circuit test techniques utilizing a bed-of-nails to make contact to each individual lead on a printed circuit board are becoming very costly and also inefficient. The need of an alternative test access fostered the development of novel test solutions like the IEEE 1149.1 boundary-scan architecture, recently extended to the mixed-signal test area by the IEEE 1149.4 Standard. At the chip level, technology advances allow to integrate functions that have been traditionally implemented on one or more complex printed circuit boards into one single integrated circuit. The development of such a system-on-chip (SOC) is based on the design technique which integrates large reusable blocks (i.e., cores) that have been designed and verified in earlier applications in practice. This design technique introduces new extremely difficult test problems due to the fact that the core user (SOC designer) in most cases does not have detailed knowledge about the core design. Further difficulties represent the problem of test access of deeply embedded cores and portability of tests between core providers, SOC designers, as well as final SOC users. An initiative for providing standardized solution has been taken by the IEEE P1500 Working Group.

Embedded system testing faces all the above problems hence it is imperative to be aware of the novel test techniques and current trends in test standardization. The paper will give a brief summary of the current state-of-the-art and give pointers for further research in this topic.

Stanislav Gruden,
Iskraemeco d.d., Kranj, Slovenia

Efficient Development of High Quality Software for Embedded Systems

New electronics products are being developed with a constantly growing pace today. The development must meet very tough criteria: short time-to-market, continuous use of currently the best available technology in order to reach high performance requirements, etc. This results in decreasing quality of the products, especially the low cost consumer electronics. The problems are most often due to the insufficiently tested software of the embedded systems used. On the other hand, there is no need to make the software optimized for performance anymore, usually the more efficient way of optimizing the overall cost and resources is just to use more powerful hardware.

In order to increase the software quality in these hard development conditions, some measures have to be taken into consideration: rigorous testing is one of them, but a lot can also be achieved by using of high level programming languages wherever applicable, making code as portable and reusable as possible, using tested other party software whenever accessible, etc.

Some techniques that can be used to make software more portable and reusable are presented. A common characteristics of these techniques is to use some of the system resources like memory or CPU time in exchange for structural organization that makes the code much easier to maintain, distribute between many developers and test. The technique of compiling and testing the code on strong personal computers or workstations before using it on a real system is described. This technique takes up some additional development resources at the beginning but saves them lately because it makes developing and testing a new code much easier, makes it portable and it is possible to have a large part of application completed even before the actual hardware is obtained.

Mohamed Akil,
Groupe ESIEE, laboratoire A2SI, Noisy le Grand Cedex, France

High-Level Synthesis based upon Dependence Graph for Multi-FPGA

The increasing complexity of signal, image and control processing algorithms in real-time embedded applications requires efficient system-level design methodology to help the designer to solve the specification, validation and synthesis problems. Indeed, the real-time and embedded constraints may be so strong that the available high performance processors are not sufficient. That leads to use, in complement of processor, the specific component like ASIC or FPGA. Several projects have developed high-level design flow that translates high-level algorithm specification to an efficient implementation for mapping onto multi-component architecture. In this paper, we present:

1. A unified model for hardware/software codesign, based on the AAA methodology (Algorithm-Architecture Adequation). In order to exhibit the potential parallelism of algorithm to be implemented, the AAA methodology is based on conditioned (conditional execution of computations) factorized (loop) data dependence graph.
2. Some simple rules that allow synthesizing both the data path and the control path of a circuit corresponding to an algorithm specified as a Conditioned and Factorized Data Dependence Graph (CFDDG).
3. The optimized implementation of CFDDG algorithm onto FPGA circuit and Multi-FPGA (partitioning), by using simulated annealing approach.
4. The resources and time delay estimation method. This method allows us to have a performance analysis for the implementation. The obtained results (resource estimation, latency estimation) are used by the optimization step to decide which implementation respects the constraints (real-time implementation which minimises the resource utilisation).
5. The results of the implementation of the matrix-vector product algorithm onto a Xilinx Multi FPGA and the software tool SynDEx which implements the AAA methodology.

Manfred Glesner,
Institute of Microelectronic Systems, Darmstadt University of Technology, Germany

System Design and Integration in Pervasive Appliances

Mark Weiser imagined the forthcoming ubiquitous computing systems as specialized elements of hardware and software, connected by means of both wired and wireless technologies. Eventually, such elements should gracefully melt into the environment and become so ubiquitous that no one will notice their presence. By weaving itself in an indistinguishable and diffuse fashion into the everyday life, pervasive technologies allow users to focus on tasks rather than tools.

In a world composed of advanced communication components, highly sophisticated sensors, smart pens and tabs, such gadgets and the design thereof have to comply with a multitude of characteristics presented throughout the talk like proactivity, transparency, ease-of-use, high-level performance and energy management, cyber foraging and surrogate request support, location and context awareness, scalability, and so forth.

On one hand, as technology shrinks and the maximum die size enlarges, integrating complete systems of continuously increasing complexity becomes possible. On the other hand, technology improvements bring with them several challenges and drawbacks. In order to cope with those problems, a multitude of design paradigms like reconfigurable architectures, platform based design, IP reuse, orthogonalization of concerns, and communication abstraction emerged during the last decade. First, this talk tries to give an insight in the challenges imposed on system design by pervasive appliances and secondly, it discusses emerging hardware architectures and design methodologies.

Contact person for the Workshop on EMBEDDED SYSTEMS
Dr. Andrej Zemva
Faculty of Electrical Engineering
Trzaska 25
Si-1000 Ljubljana, SLOVENIA
tel. +386 1 4768346, fax. +386 1 4264630
email: Andrej.Zemva@fe.uni-lj.si